The present invention relates to a semiconductor device for a super high frequency and, more particularly, to a Schottky barrier type field effect transistor and a method of manufacturing the same.
FIG. 1A to 1C show manufacturing steps of a conventional Schottky barrier gate field effect transistor (SBGFET). This SBGFET shown in FIG. 1C has a semi-insulation substrate 10 of GaAs. Source and drain regions 12 and 14 are formed in the surface area of the substrate 10. A channel region 16 of this SBGFET is formed between the source and drain regions 12 and 14. A gate electrode 18 is formed on the channel region 16 in Schottky contact therewith. The source, drain and channel regions 12, 14 and 16 include N-type impurities, and the impurity concentrations in the regions 12 and 14 are higher than that in the region 16.
Generally, the operating characteristic of the SBGFET in the high frequency range is easily influenced by a parasitic resistance. In particular, in the case of the above SBGFET, the impurity concentration in the channel region 16 is lower than those in the source and drain regions 12 and 14, so that the operating characteristic depends upon a source parasitic resistance RS that is proportional to a distance LS between the source region 12 and the gate electrode 18 and upon a drain parasitic resistance RD that is proportional to a distance LD between the gate electrode 18 and the drain electrode 14. In order to allow this SBGFET to have a good transfer conductance, it is necessary to set the distances LS and LD to be short and thereby to limit the source and drain parasitic resistances RS and RD to sufficiently low values. In addition, in order to permit the SBGFET to have a good gate withstanding voltage, it is necessary to set the distance LD to be long. As a result, to manufacture the SBGFET with high performance, the distances LS and LD have to be set as short as possible within a range where a sufficient gate withstanding voltage is secured.
A method of manufacturing the SBGFET of FIG. 1C will now be described. First, N-type impurities of a low concentration are doped in the GaAs semi-insulation substrate 10, thereby forming an N-type region 16A shown in FIG. 1A. Thereafter, the N-type impurities of a high concentration are ion-implanted into the N-type region 16A and annealed, so that the N.sup.+ -type source and drain regions 12 and 14 shown in FIG. 1B are formed. At this time, a part of an N-type region 16A remaining between the source and drain regions 14 and 16 is used as the channel region 16. The surfaces of the source, drain and channel regions 12, 14 and 16 are covered by a photo resist through an SiO.sub.2 film used as a spacer. Further, parts of the photo resist and SiO.sub.2 film are etched using a mask pattern in order to expose the central portion of the channel region 16. A metal layer is formed on the photo resist and on the exposed portion of the channel region 16. After that, the metal layer is removed with use of the lift-off technique, excluding the portion on the junction with the channel region 16, due to the melting of this photo resist subjected to the etching process. The metal layer on the channel region 16 is used as the gate electrode 18.
On the other hand, in the above SBGFET, the position of the gate electrode 18 is specified by the mask pattern, so that the distances LS and LD of this SBGFET are influenced due to an error in mask alignment. If the distances LS and LD are set without taking account of this error, a number of defective SBGFETs, each having a low gate withstanding voltage or low transfer conductance, will have been produced due to the actual manufacturing. To prevent the reduction in yield, the distances LS and LD in the SBGFET shown in FIG. 1C have been conventionally set to long values of about 2 .mu.m.
On the other hand, FIG. 2B shows a conventional SBGFET which is produced by another manufacturing method than the SBGFET of FIG. 1C. In the SBGFET of FIG. 2B, N-type impurities of a low concentration are doped into the GaAs semi-insulation substrate 10, thereby forming the N-type region 12A shown in FIG. 2A. Next, as shown in FIG. 2A, a gate electrode 20 is formed on the N-type region 12A, and the N-type impurities of a high concentration are ion-implanted into the N-type region 12A using the gate electrode 20 as a mask and are annealed. Thus, as shown in FIG. 2B, N.sup.+ -type source and drain regions 22 and 24 are formed in the surface area of the GaAs semi-insulation substrate 10. A part of the N-type region 12A remaining between the source and drain regions 22 and 24 is used as a channel region 26.
In the SBGFET of FIG. 2B, the source and drain regions 22 and 24 are formed for ion-implantation by means of a self-alignment method using the gate electrode 20 as a mask. Due to this, the SBGFET in which the parasitic resistances RS and RD have enough small values can be manufactured without considering the error in mask alignment, as in the SBGFET of FIG. 1C. However, in this SBGFET, there is a case where the impurities of a high concentration are laterally diffused at the time of annealing, so that the source region 22 comes into contact with the drain region 24. Consequently, deterioration in the gate withstanding voltage and variation in the threshold voltage will occur.